The present invention generally relates to telecommunications and more specifically to providing a single stage PLL circuit that can generate fine granularities of frequencies.
Phase lock loops (PLLs) are used to synthesize frequencies. A reference frequency from a reference clock is generally received and various output frequencies can be synthesized. Generally the frequencies that can be synthesized are limited to integer multiples of the reference frequency. The output frequencies can then be divided. The dividers are implemented in digital logic and are limited to integer values. This limits the frequencies that can be generated by PLL systems.
The lower the frequency of the reference clock, the finer the granularity of output frequencies that can be achieved. This is due to having a greater choice of multipliers and dividers without saturating a voltage controlled oscillator (VCO) frequency. However, a PLL cannot typically lock to a low frequency reference clock. For example, using a 256 Hz reference clock, producing output frequencies in 1 Hz granularity is not possible for certain ranges. In other words, a full range of frequencies cannot be generated using a single stage PLL with the 256 Hz reference clock.
Accordingly, if a frequency, such as, 128003 is desired, the only frequencies that can be generated are 128000 and 128008 because the granularity is 8 with frequencies between 66536-131072. Thus, frequencies can be generated in increments of 8 Hz in that range of frequencies. For devices that require finer granularities of output frequencies, users are limited to using multiple stage PLLs. However, multiple stage PLLs increase complexity on a chip or a board and also increase the cost of producing the chip or the board. With space on a chip or a board being very valuable, it may not be desirable to have a multiple stage PLL.